Copyright

 Copyright



   

LSI Products I was involved in the design

(A) NEC, Japan

LSI
Product

Year

Architecture
Specification

Logic
Design

Firmware
Design

Breadboard
Design

Breadboard
Debug

Logic
Conversion

Computer
Simulation

Mask Layout
Design

System
Evaluation

LSI Test

31

1971

customer

customer

hardwired

customer

customer

100%

100%

contractor

0%

0%

32

1971

customer

customer

hardwired

customer

customer

100%

100%

contractor

0%

0%

33

1971

customer

customer

hardwired

customer

customer

100%

100%

contractor

0%

0%

XX

1971

customer

customer

hardwired

customer

customer

100%

0%

contractor

abandoned

abandoned

Customer's design LSIs

[31, 32, 33]
Mr. Tomoyo Ichikawa of Eiko Business Machine, Inc. designed the original logic for 8 digits desk-top calculator with Eiko proprietary printer and divided the entire logic into five LSIs nick-named 31, 32, 33, 34, and 35. Soon after I started working at NEC in June, 1971, I took charge of 31, 32, and 33 that functioned as Central Processing Unit, data memory, timing generator, and so forth. I completed the logic conversion from the original logic schematics given by Eiko Business Machine to NEC logic modules (blocks) to ease the mask layout utilizing building blocks scheme as well as the computer simulation. 34 and 35 were Printer Control Unit and handled by Mr. Shimizu of NEC. Mr. Shimizu took over system evaluation and LSI test for all the five LSIs later on.

The computer simulation for LSI was an emerging technology intensively using main frame at that time. The net list and simulation vectors were punched on IBM 80 column punch cards line by line.

[XX]
XX was a single-chip 8 digits desk-top calculator LSI designed by a certain independent design house based on development request from NEC. NEC did not have sufficient ability to design desk-top calculator LSI at that moment. Although I was not a person in charge of the project, I was requested to complete the logic conversion because only a limited number of LSI designers was able to do the work. Because NEC strongly promoted the XX project, a most experienced contractor was assigned for the mask layout as well. However, the die size after the actual mask layout had become larger than 5mm x 5mm due to a lot of internal wire connections derived from the hard-wired random logic design. At that time, it was common knowledge that the yield became zero (no good die per silicon wafer) if the die size became beyond 5mm x 5mm.

At the next stage, I was requested to try to divide the entire logic into two LSIs (this means that it is not a single-chip LSI). My conclusion was “Unrealistic and Impossible” because the number of LSI pins easily went beyond 28 pins due to a lot of interconnects. The maximum number of LSI pins available was 28 at that time because of the constraint of LSI packaging technology.

Consequently, the project XX was eventually abandoned.

Mr. Atsuyoshi Ouchi, a manager of NEC Integrated Circuit division, decided to pay the compensation for the development to the design house although NEC did not make anything and any profit from XX. Mr. Kurokawa, a section manager, applauded the reaction saying “It is good for future”.

This event triggered two big projects for developing 8 digits single-chip desk-top calculator LSI (mPD271) and 12 digits multiple-chip desk-top calculator LSI chip-set (mPD281, mPD282, mPD261, mPD262, mPD264) to be designed by NEC's own efforts.

Mr. Tomihiro Matsumura, a manager of second circuit technology department, promptly organized the LSI development projects in March, 1972, and held the kick-off meeting. Although I did not know why this happened, probably unfortunately, I had sat down a seat just in front of Mr. Matsumura of a square desk for 5 x 6 people (Yamamoto, Shiraishi, Matsumura, Takashima, Kurokawa vs. Tanaka, Ariga, Takai, Oguchi, Maehashi, Oura). As soon as I sat down, Mr. Matsumura immediately started arguing me saying, “Oguchi-kun, although you may be a rookie......” He disputed my reactions and resolutions concerning aforementioned XX LSI development. He seemed not to know the whole course of events that most people sitting there knew well. I gazed at Mr. Takashima sitting left beside Mr. Matsumura considering that he tried to evade his responsibility (this was the first job for him just after appointed to a supervisor.) and transferred it all to me. Because I believed that I did the best and the original design had fatal weak point of hard-wired design approach (Moreover, this is not my own design!), I sat still thinking that “This is My Way”.

Tomorrow morning, Mr. Takai and Ariga who were actually people in charge of XX product came to me and told that “Just leave it”. Mr. Shiraishi, a manager of device design section, also came and told that “After you left, I clearly defended you with the truth. I usually say what I want to say.” This was his nature derived from his origin of Kyusyu island that most Japanese did not have.

 

LSI
Product

Year

Architecture
Specification

Logic
Design

Firmware
Design

Breadboard
Design

Breadboard
Debug

Computer
Simulation

Mask Layout
Design

System
Evaluation

LSI
Test

mPD282

1972

30%

100%

hardwired

50%

10%

100%

100%

100%

100%

mPD940

1973

100%

100%

50%

20%

0%

100%

100%

100%

100%

mPD941

1974

derivative

derivative

100%

derivative

100%

100%

derivative

100%

100%

mPD942

1974

derivative

derivative

100%

derivative

100%

100%

derivative

100%

100%

mPD943

1974

derivative

derivative

100%

derivative

100%

100%

derivative

100%

100%

mPD1201

1975

100%

100%

50%

0%

0%

100%

100%

100%

100%

mPD1202

1975

derivative

derivative

100%

derivative

100%

100%

derivative

100%

100%

mPD1203

1976

derivative

derivative

100%

derivative

100%

100%

derivative

100%

100%

mPD1205

1976

100%

100%

80%

50%

100%

0%

0%

0%

0%

mPD777

1977

50%

90%

20%

90%

0%

0%

100%

0%

0%

mPD7220

1981

100%

100%

hardwired

100%

100%

0%

5%

100%

0%

mPD7220A

1983

derivative

100%

hardwired

100%

100%

0%

50%

100%

0%

mPD72120

1987

100%

0%

0%

0%

100%

0%

0%

100%

0%

NEC original design (not based upon reverse engineering as well as customer's design)

[mPD282]
I fully took charge of mPD282, a CPU with memory LSI for 12 digits 1 memory desk-top calculator. The logic design completed less than one year later I joined NEC in 1971. mPD282 along with mPD281 is the first logic LSI that NEC originally designed from scratch.
The development project was initiated by powerful direction of Mr. Tomihiro Matsumura, a department manager, due to the abortion of single-chip LSI design (XX as mentioned above) for 8 digit calculator that NEC requested to external independent design house.
I was so lucky because I was able to build broad LSI design expertise through the actual
mPD282 design in very early stage of my engineering life.

Functions
- 4 x 64 bits (for 12 digits BCD data with one overflow digit + decimal point BCD data digit + control digit + sign digit) ratio-less shift registers
- 1 x serial BCD full adder/subtractor with carry calculation
- Instruction decoder
- Judge output and ROM code inputs to/from mPD281
- Data & timing outputs to mPD261 segment decoder
- Timing input/output to/from
mPD262 digit timing generator
- Data output & input to/from
mPD264 extended memory
- Display data outputs to 8 segment fluorescent digit display tubes

Process & Design
10m P channel metal gate E/E MOS using building block mask layout, VGG = -24V, VDD = -12V, GND = 0V, Two phase clocks (/f1, /f2), Capacitive dynamic shift registers and transmission gate design

System structure
The 12 digits 1 memory desk-top calculator system consist of a mPD281 (ROM + address sequencer + keyboard decoder; 24 pin ceramic DIP LSI), a mPD282 (CPU + memory; 28 pin ceramic DIP LSI), a mPD261 (8 segment decoder; 20 pin plastic DIP MSI), a mPD262 (digit timing generator; 20 pin plastic DIP SSI). mPD264 (extended memory; 20 pin plastic DIP MSI) can be attached to increase the number of data memories.

Abbreviations
CPU (Central Processing Unit), BCD (Binary-Coded Decimal), ROM (Read-Only Memory), DIP (Dual-Inline Package), E/E (Enhancement mode for load MOS transistor/Enhancement mode for gate MOS transistor), MOS (Metal Oxide Semiconductor), VGG (Voltage supplied to Gate of load MOS transistor), VDD (Voltage supplied to Drain of load MOS transistor), GND (Ground voltage), LSI (Large-Scale Integration), MSI (Medium-Scale Integration), SSI (Small-Scale Integration)

Although everybody expected that the mask-layout of the mPD282 is done by a contractor as usual, I started mask-layout design as soon as I completed logic design and computer simulation. Mr. Matsumura came to me and told mischievously with smile, “You are doing the mask-layout with strong guts, aren't you?”
I experienced work through the night three times for breadboard debug and x200 film cut mask base inspection to be done before ordering physical photo mask.
Mr. Oura taught me how to handle LSI testers, ASR33 teletypewriter, paper tape, and updating the paper tape contents by using special tools.

update in progress

[mPD940 - mPD943]
update in progress

[mPD1201 - mPD1203]
update in progress


[mPD1205]
update in progress


[mPD777]
update in progress


[mPD7220 - 7220A]
update in progress


[mPD72120]
update in progress


Remarks :
(A) Work categories below are eliminated from the table.
 (1) Inspection such as designs at various stages
 (2) Customer visit and support
 (3) Dual-port DRAM related
 (4) Thesis and seminar
 (5) Research
 (6) Management and presentation
 (7) Any other miscellaneous side works

(B) The trial productions were always handled by device design team using photo masks I ordered to Toppan Printing or Dai Nippon Printing as a result of mask layout design.

(C) LSI testers I used for trial production and evaluation were MH-134 (Minato Tsushinki), MH-152 (Ando Electric), and MH-200 (Ando Electric).
 (1) For wafer check (P/W test), I ordered probe cards based upon pin connection and bonding pads' position information.
 (2) For screening test (選別) and warehousing test (入庫), I ordered DUT (Device Under Test) boards.
 
(3) For BT (Bias Temperature) test, I ordered BT boards.
 (4) For system level test (実装), I made manually-driven system level testers and test programs for automatic system level testers designed as a result of co-operation with automation department, later on (applied to mPD282 to mPD1205, 1972 - 1976).


(B) Chips & Technologies, USA

LSI
Product

Year

Architecture
Specification

Logic
Design

Firmware
Design

Breadboard
Design

Breadboard
Debug

Computer
Simulation

Mask Layout
Design

System
Evaluation

LSI
Test

82C455

1988

100%

100%

hardwired

none

none

100%

gate array
(Toshiba/LSI Logic)

100%

0%

82C456

1989

100%

100%

hardwired

none

none

100%

gate array
(Toshiba)

100%

0%

82C457

1990

100%

100%

hardwired

none

none

100%

gate array
(Toshiba)

100%

0%

[82C455 - 82C457]
update in progress


(C) ASCII of America, USA

LSI
Product

Year

Architecture
Specification

Logic
Design

Firmware
Design

Breadboard
Design

Breadboard
Debug

Computer
Simulation

Mask Layout
Design

System
Evaluation

LSI Test

DA7290

1993

0%

0%

hardwired

none

none

0%

gate array
(VLSI Technology)

100%

gate array

HD814102

1994

derivative

derivative

hardwired

none

none

0%

gate array
(Hitachi)

100%

gate array

[DA7290 - HD814102]
update in progress


(D) Auctor Corporation, USA

LSI
Product

Year

Architecture
Specification

Logic
Design

Firmware
Design

Breadboard
Design

Breadboard
Debug

Computer
Simulation

Mask Layout
Design

System
Evaluation

LSI Test

YY

1996

100%

100%

100%

50%

80%

80%

gate array

abandoned

abandoned

[YY]
update in progress

(E) SanDisk, USA

LSI
Product

Year

Architecture
Specification

Logic
Design

Firmware
Design

Breadboard
Design

Breadboard
Debug

Computer
Simulation

Mask Layout
Design

System
Evaluation

LSI Test

Bishamon

2000

100%

100%

100%

80%

100%

100%

gate array

abandoned

abandoned

[Bishamon]
update in progress

About Litigation between Western Digital & Toshiba  New

Joint Venture of SanDisk and Toshiba
SanDisk acquired by Western Digital and Toshiba mutually established joint venture concerning NAND flash memory development & manufacturing at Yokkaichi, Mie, Japan in 2000.
For last 17 years, the two companies have been investing a lot, $XY billion, in proportion to Toshiba (51%) and SanDisk (49%) beyond five generations of factory expansion, etc..

As a result of the joint development, San Disk and Toshiba co-authored papers (theses) for prestigious IEEE (Institute of Electrical and Electronics Engineers) ISSCC (International Solid State Circuit Conference) and 13 theses were accepted (See “ISSCC Papers Co-aurthored.pdf”).
SanDisk and Toshiba co-assigned US patents and 123 patents were registered (See “US Patents Co-assigned.pdf”).


Western Digital's Concerns
Based upon the long term successful cooperation, Western Digital expressed help bailing out Toshiba facing with fatal financial problem (See “WD Willing to Help Toshiba.pdf”), 4/25/2017.
Western Digital CEO Steve Milligan kindly stated concerning Toshiba problem at WD 2017 third fiscal quarter conference call (Listen to “Milligan Comment about Toshiba” and read ”Dictation of Milligan Comment”), 4/27/2017.


Sanjay Mehrotora & Khandker Quader
The joint venture was initiated by Sanjay Mehrotora (Vice president R&D, in those days) who also requested SanDisk acquisition to Western Digital in August 2015 as President & CEO of SanDisk.
Khandker Quader led flash memory design cooperating with Toshiba.


The two people already left SanDisk (See “Sanjay & Khandker.pdf”)

Khandker became President & CEO of SK Hynix Memory Solutions which is US subsidiary of SK Hynix in June, 2013.
Lawsuit against SK Hynix was filed by SanDisk and Toshiba in March, 2014 (See “Lawsuit against SK Hynix.pdf”).
Khandker left SK Hynix Memory Solutions in June, 2014, during the lawsuit.

Sanjay became board member of Western Digital for a while. Then, Sanjay became President & CEO of Micron Technology in May, 2017.
Micron Technology acquired Lexar Media, one of competitors of SanDisk flash memory business, in 2006.
Micron Technology fully acquired Elpida Memory, a Japanese sole DRAM manufacturer merged in NEC (Nippon Electric Company) and Hitachi, in 2013 (Go to “https://www.micron.com/about/about-the-elpida-acquisition”).


Optimum Settlement (My opinion)
Toshiba is now seeking funding group of
<INC
J: Innovation Network Corporation of Japan; 産業革新機構, Bain Capital, & SK Hynix>.
The presence of Korean SK Hynix is irrelevant due to SK Hynix past behavior that had tended to steal flash memory related technology from joint venture of SanDisk and Toshiba (See “Lawsuit against SK Hynix.pdf”).

Fundamental negotiation efforts made by Toshiba management team looks irrational and incoherent due to lack of technical knowledge and management experience.

Optimum settlement is to make funding group of
<INCJ: Innovation Network Corporation of Japan; 産業革新機構, Bain Capital or other appropriate US or Japan venture capitals (Kohlberg Kravis Roberts (KKR; http://www.kkr.com/)), & Western Digital>.
Western Digital leads and manages entire flash memory business after the funding.
 
ATL (Antitrust Law;
独占禁止法) intentionally being apprehended by Toshiba and supported banks will not be governed (needless fear) based upon the historical fact of Micron Technology acquisition of Elpida Memory.
Unlike Micron Technology acquisition, Western Digital adds only partial shares (present 49% + 51%/Z) as well.

Annotation: Numerical value of X, Y, and Z above means “not fixed” or "fixed in future".


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